🚦 Traffic Light Controller (FSM in Verilog)

📌 Project Overview

This project implements a traffic light controller using a Finite State Machine (FSM) in Verilog.
The traffic light cycles through traffic flows for varios routes, with each light active for a fixed number of clock cycles.

The design models a Moore FSM, where outputs (light signals) depend only on the current state.

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▶️ Simulation

1. Compile the design and testbench using your Verilog simulator (e.g., Icarus Verilog, ModelSim, or Vivado).
2. Run the simulation and generate a waveform (.vcd) file.
3. Open the waveform in GTKWave (or another viewer) to visualize states and light outputs.