system-verilog-testbench

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Here are 8 public repositories matching this topic...

SACHINUR17 / VLSI-Design-Verification-Projects

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This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Updated May 23, 2026
SystemVerilog

muhammadtalhasami / sv_verilator

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System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

verification verilog systemverilog testbench verilog-hdl verilator- system-verilog-testbench verilator-testbench

Updated Jul 10, 2024
C++

theteamonk / Dual-Port-RAM-4096x64

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Dual Port RAM - Verification in System Verilog and Functional Coverage

design-verification functional-coverage system-verilog-testbench

Updated Jul 27, 2025
SystemVerilog

DorsaAk / MIPS-single-cycle-processor

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📚"Major Course Assignment": MIPS Single-Cycle Processor: Implementation in Verilog + Confirmation on Zynq SoC via Xilinx Vivado

fpga computer-architecture modelsim verilog-hdl zynq-7010 major-project system-verilog-testbench

Updated Jun 20, 2026
Verilog

DorsaAk / combo_fp_adder

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🧪"A Simple Hands-On Project": A fully combinational Verilog implementation of IEEE-754 single-precision floating point addition

computer-architecture modelsim fpga-soc verilog-hdl zynq-7010 hands-on system-verilog-testbench

Updated Jun 20, 2026
Verilog

nithinnj93 / vlsi-smart-irrigation-system

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VLSI-oriented Smart Irrigation Controller featuring Verilog RTL modules, self-checking testbenches, FSM-based control, and planned ESP32 IoT integration.

fpga verification embedded-systems rtl verilog uart vlsi system-verilog verilog-hdl digital-design verilog-project vlsi-design vlsi-designing rtl-design hardware-design system-verilog-codes system-verilog-testbench system-verilog-hdl

Updated Jul 17, 2026
Verilog

DorsaAk / serial_transceiver_moore_fsm

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🧪"A Simple Hands-On Project": A simple UART-inspired serial transceiver implemented as a Moore FSM (An exercise of typedef enum, timescale and signed/unsigned numbers in Verilog)

modelsim digital-design hands-on system-verilog-testbench system-verilog-hdl