RTL to GDSII implementation of a parameterized Universal Counter using OpenLane and SKY130
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Jul 13, 2026 - Verilog
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sky130-pdk
Here are 13 public repositories matching this topic...
EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation
linux makefile systemverilog bash-script verilog-hdl yosys asic-verification openroad asic-design rtl-design fpga-prototyping rtl-verification rtl-to-gdsii sky130-pdk
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Jul 5, 2026 - SystemVerilog
Synthesizable RV32IM Audio SoC featuring a centralized AMBA AXI4-Lite Router Matrix, AXI-to-APB Bridge, 1KB Data SRAM, and PWM engine. Timing-closed and physical layout verified via OpenLane (Sky130).
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Jul 16, 2026 - Verilog
Simple Systolic array implementation
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May 15, 2026 - Verilog
Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.
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Jan 17, 2026 - SystemVerilog
End-to-End ASIC Design of an 8×32 Synchronous FIFO featuring Verilog RTL design, assertion-based verification in Vivado, and RTL-to-GDSII implementation using OpenLane with the SKY130 PDK.
asic verilog systemverilog fifo vlsi klayout digital-design gdsii physical-design rtl-design openlane sky130-pdk static-timing-analysis--sta
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Jul 13, 2026 - Verilog
Open Integrated Circuit Library — a searchable catalog of silicon-proven IC designs from open PDKs (SKY130, IHP SG13G2, GF180). Auto-discovers and classifies designs from GitHub/GitLab.
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Jul 7, 2026 - Python
Design of a 10-bit R-2R DAC using the open-source SkyWater 130nm PDK. Includes schematics, layout files, and a Python environment for metric evaluation (for educational purposes).
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Apr 30, 2026 - Python
Data-driven EDA and ML-based predictive modelling of real VLSI design metrics from an OpenLane RTL-to-GDSII flow. 8-bit ALU on Sky130 PDK.
python machine-learning scikit-learn pandas seaborn data-analytics matplotlib vlsi openlane sky130-pdk
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May 9, 2026 - Jupyter Notebook
Automated SKY130 DRC flow using KLayout, Python, and TCL to run custom design-rule checks, parse XML results, and generate an HTML violation dashboard.
python automation tcl eda gds vlsi klayout silicon ic-design html-dashboard layout-verification standard-cells physical-verification sky130-pdk design-rule-checking open-source-pdk
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May 14, 2026 - Python
RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.
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Apr 2, 2026
8-bit Signed Radix-4 Modified Booth Multiplier with 16-bit Carry Lookahead Adder | RTL to GDSII | Verilog | OpenLane | Vivado | Cadence
asic fpga vivado computer-architecture verilog-hdl yosys digital-design vlsi-design rtl-design booth-multiplier openlane sky130-pdk
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Jul 12, 2026 - Verilog
Complete RTL-to-GDSII implementation of a parameterizable 8-bit ALU using Verilog, Yosys, OpenSTA, OpenLane, Magic, KLayout, and the Sky130 Open-Source PDK.
asic rtl vlsi verilog-hdl yosys klayout digital-design gdsii physical-design opensta openlane magic-vlsi sky130-pdk
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Aug 4, 2026 - Verilog
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