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hardware-synthesis

Here are 17 public repositories matching this topic...

Verilean / sparkle

A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.

hdl formal-verification risc-v hardware-synthesis lean4

Updated Aug 7, 2026
Lean

gussmith23 / lakeroad

FPGA synthesis tool powered by program synthesis

fpga dsp program-synthesis hardware-synthesis technology-mapping

Updated Dec 15, 2025
Racket

tongplw / HW-Syn-Lab

⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

holoso

Zubax / holoso

Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.

fpga hls dsp verilog pipelining hdl high-level-synthesis softcore hardware-synthesis nisc zisc

Updated Aug 6, 2026
Python

srijavuppala / rtl_agent

Agentic RTL generation pipeline: text/PDF/audio/video → Spec IR → Two-Oracle agent → verified SystemVerilog (GLSVLSI 2026)

eda multi-agent gemini rtl verilog verilog-hdl hardware-synthesis rtl-generation llm agentic-ai

Updated Jun 19, 2026
Jupyter Notebook

omgbox / mbe-engine

The Morphic Bitstream Engine (MBE) - A revolutionary computing architecture that processes raw binary data without traditional limitations

Updated Jul 24, 2026
Python

benallard / nextpnr-turingtumble

A nextpnr arch definition for the TuringTumble board game.

fpga yosys hardware-synthesis turing-tumble nextpnr

Updated Nov 5, 2022
Verilog

natTP / 2110363-hw-syn-lab

Code written during 2110363 HW SYN LAB I course, Academic Year 2021, Chulalongkorn University.

fpga verilog hardware-synthesis

Updated Feb 2, 2022
Verilog

EngineersBox / MCV

Verilog to redstone compiler + synthesiser for Minecraft

minecraft redstone verilog hardware-synthesis

Updated Mar 5, 2023

kraftpunk97 / 8-bit-RISC-Microprocessor

An 8-bit RISC Microprocessor made for my Embedded Systems course.

hardware verilog microprocessor risc xilinx-vivado hardware-synthesis

Updated Jul 11, 2024
Verilog

kazakma / ai_fpga

Выпускная квалификационная работа: генератор аппаратных блоков функций активации для FPGA

fpga verilog fixed-point sat-solver smt-solver digital-design cyclone-iv hardware-synthesis intel-fpga activation-functions

Updated Jul 21, 2026
Verilog

ovenror / librhdl

a hardware synthesis library for Minecraft Redstone circuits

minecraft redstone hardware-synthesis

Updated May 20, 2026
C++

InvincibleJuggernaut / ALU

Design for 4 bit ALU with essential logical and arithmetic modules.

verilog hardware-designs hardware-description-language hardware-synthesis arithmetic-logic-unit

Updated Oct 29, 2021
Verilog

JuhoArtturiHemminki / GTCSYN

Non-dissipative computational engine implementing the Unitary Transduction Invariant (ΔI · Φ = W_rec). Bypasses the Landauer limit via Golden Ratio (Φ) phase-synchronization. Eliminates thermal resonance by re-channeling entropy into recirculative work. Written in Rust.

Updated Apr 2, 2026
Rust

SCLW / hardware-lfsr

CPU-free hardware sound synthesis and multichannel spatialization with linear feedback shift registers (LFSRs).

spatial-audio sound-art electronic-music generative-music lfsr pseudorandom hardware-synthesis multichannel-audio tiny-tapeout

Updated Jul 6, 2026

nicolasbenatti / hw-convolutional-encoder

Digital Logic Design project at Politecnico di Milano

vhdl hardware-synthesis hardware-design

Updated Jun 23, 2024
VHDL

rbostandoust / CapNet-Accelerator

Hardware accelerator for Capsule Neural Networks

hardware-synthesis capsule-neural-networks hardware-accelerator

Updated Aug 8, 2023
Python

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