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  1. Five-Stage-Pipelined-CPU-Verilog Five-Stage-Pipelined-CPU-Verilog Public

    16-bit Five-Stage Pipelined CPU in Verilog with Forwarding, Hazard Detection, Branch Handling, Pipeline Flush and Performance Monitoring.

    Verilog

  2. configurable-cache-memory-subsystem configurable-cache-memory-subsystem Public

    Configurable Cache Memory Subsystem with Complete RTL-to-GDSII Implementation using OpenROAD.

    Verilog 1

  3. AHB-TO-APB-BRIDGE AHB-TO-APB-BRIDGE Public

    RTL implementation of an AMBA AHB-to-APB Bridge in Verilog HDL with functional simulation, synthesis results, architecture diagrams and comprehensive documentation.

    Verilog