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[BUG] JVT address calculation truncates the 8-bit table index
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3442 In openhwgroup/cva6;[BUG] Zcmt table jump (cm.jt/cm.jalt) does not clear bit 0 of the target
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3441 In openhwgroup/cva6;[BUG] RV64 Zcmp PUSH/POP expansion uses 4-byte offset increments, causing overlapping accesses and incorrect SP adjustment
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3440 In openhwgroup/cva6;[BUG] frontend/instr_scan incorrectly decodes reserved C.JR and C.EBREAK as valid RVC jump instructions
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3439 In openhwgroup/cva6;[BUG] cbo.inval does not stall a following load to the same cache block
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)Status:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3432 In openhwgroup/cva6;[BUG] Zicbom CBO.INVAL/CLEAN/FLUSH are permission-checked as plain stores, causing spurious store faults on read-only / clean / read-only-PMP regions
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3431 In openhwgroup/cva6;[BUG] PTW issues a D-cache request for a PMP-denied PTE before enforcing PMP
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3430 In openhwgroup/cva6;[BUG] csr_regfile: with dcsr.step set, an instruction that traps enters Debug Mode only after the trap handler has started
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:DEBUGDebug modeDebug modeStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3429 In openhwgroup/cva6;[BUG] cva6_mmu: a pure G-stage (vsatp=Bare, Sv39x4) instruction-fetch address with bits [63:41] set raises INSTR_PAGE_FAULT instead of INSTR_GUEST_PAGE_FAULT
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3428 In openhwgroup/cva6;[BUG] cva6_mmu: the HLV translation override leaks into the next access's DTLB lookup, so an ordinary HS load reads a guest-chosen physical address
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3427 In openhwgroup/cva6;[BUG] cva6_mmu: identical two-stage access reports cause 15 on a DTLB miss and cause 23 on a DTLB hit
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:NewNewly created issue, nobody has looked at it yet.Newly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3426 In openhwgroup/cva6;[BUG] HLVX permission rule is wrongly applied to the G-stage check on VS-stage page-table reads (cva6_ptw.sv)
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)PARAM:MMUMMU relatedMMU relatedStatus:In ProgressWork on this issue has started, but is not complete.Work on this issue has started, but is not complete.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3425 In openhwgroup/cva6;