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MAIN LINK: You can download the complete RVfpga packages from Imagination Technologies IUP.
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You can access the Computer Architecture with an Industrial RISC-V Core [RVfpga] edX MOOC, based on RVfpga.
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RISC-V International recommends RVfpga in their Learning Materials GitHub and for Training and Certification in RISC-V.
This repository provides materials from a range of RVfpga-based teaching experiences, primarily conducted during the 2024-25 and 2025-26 academic years.
We first show how we adapted and used the RVfpga: Understanding Computer Architecture and the RVfpga-SoC packages provided by Imagination Technologies, as well as the Ripes simulator, in the labs of three courses instructed at the University Complutense of Madrid (UCM).
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Computer Fundamentals (second semester of year 2024-25): This is a first-year course in the Computer Science degree program at UCM. In folder Computer_Fundamentals of this repository you can find all the materials used in the course. Since this is an introductory course, we only use Ripes in the labs.
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Computer Organization (first semester of years 2024-25, 2025-26 and 2026-27): This is a second-year course in the Computer Science degree program at UCM. In folder Computer_Organization of this repository you can find part of the materials (mainly the labs) used in the course. For the labs, we use a combination of Ripes and RVfpga-based exercises.
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Integrated Systems Architecture (second semester of years 2024-25 and 2025-26): This is a fourth-year course in the Electronics and Communication Engineering degree program at UCM. In folder Integrated_Systems_Architecture of this repository you can find part of the materials (mainly the labs) used in the course. Since this is an advanced course, we mainly use RVfpga-based labs.
We also participated in the Master de Formación Permanente en Sistemas Microelectrónicos Basados en Arquitecturas Abiertas (first semester of year 2024-25) at the University of Castilla-La Mancha (UCLM). Specifically, within the course Diseño de Microcontroladores en Hardware Abierto, we taught an entire two-week-long module based on RVfpga. You can find the details in the following folder: Design_Microcontrollers_Open_Hardware
In years 2024-25 and 2025-26, we instructed a microcredential as part of a joint effort between UCM and OpenChip. This is the official webpage of the 2025-26 course: RISC-V: Architecture and Design based on Commercial VeeR Cores on FPGA. Here, you can find all the materials used in the 2025-26 course: RVfpga_Microcredential
Finally, it should be highlighted that a number of Bachelor's and Master's theses at UCM were developed using RVfpga, among which the most notable are:
- Floating-point extensions for the SweRV EH1 core
- FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
If you're interested in learning more about the details of the RVfpga course, check out our paper published at IEEE Access in January-2026:
In the following links you can also find many videos that illustrate different topics of RVfpga.
- Videos at YouTube Channel: RVfpgaVideos
- Imperial College WS 2022: LondonWS
- IUP Video Library:
RVfpga provides both simulation and hardware-based methods for using and analyzing the RVfpga core, SoC, and its peripherals.
The following figure shows an overview of these tools using the EL2 SoC and a Nexys A7 FPGA board.
All tools share a common back-end —the VeeRwolfX SoC code— but use different front-ends.
- Execution on the physical board:
The VeeRwolfX SoC can run in hardware on supported FPGA boards. Default configurations are provided with the packages, but users can also generate new bitstreams using Vivado. Instructions for generating the bitstream and running on these boards are available at RVfpga: Understanding Computer Architecture and in some of the above courses (such as Integrated_Systems_Architecture_24-25 or Design_Microcontrollers_Open_Hardware_24-25). RVfpga supports three FPGA boards: Nexys A7, Basys 3, and Boolean.
- Execution in simulation:
RVfpga includes several SoC simulation tools (the first three are based on Verilator). Instructions for running these simulators are available at RVfpga: Understanding Computer Architecture and in some of the above courses (such as Computer_Organization_25-26):- RVfpga-ViDBo: simulates the RVfpga System on a Virtual Development Board, including communication with peripherals.
- RVfpga-Pipeline: visualizes the execution of instructions through the VeeR EH1 or EL2 pipeline.
- RVfpga-Trace: records internal SoC signals while running a program and visualizes them with GTKWave.
- RVfpga-Whisper: a RISC-V Instruction Set Simulator.
With these tools, the complete RVfpga course can be followed without a physical board, at no cost.
Internally, all SoC simulators use Verilator, which translates the Verilog SoC into C++ code that is then compiled and executed to simulate RISC-V programs.
Default simulation binaries are included in the RVfpga package, but users can also generate new ones using Verilator.
Sources and compilation instructions can be found in several places:
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Course-provided packages (two versions available):
- SimulatorsAndProjects_24-25
After extracting the archive, the three simulators can be found in:- RVfpga-ViDBo:
Simuladores_EC_24-25/RVfpga/verilatorSIM_ViDBo - RVfpga-Pipeline:
Simuladores_EC_24-25/RVfpga/verilatorSIM_Pipeline - RVfpga-Trace:
Simuladores_EC_24-25/RVfpga/verilatorSIM_Trace
- RVfpga-ViDBo:
- SimulatorsAndProjects_25-26
Same as the previous version, but including an enhanced RVfpga-Pipeline simulator.
- SimulatorsAndProjects_24-25
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RVfpga course v3.0: RVfpga: Understanding Computer Architecture
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edX MOOC: RVfpga-based MOOC
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Academic papers associated with RVfpga
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Older versions of RVfpga-ViDBo and RVfpga-Pipeline are also available on GitHub: SimulationTools