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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

fix(StoreUnit): fix illegalIssue of unalign store module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6322 opened Aug 4, 2026 by weidingliu Member Loading…
1
fix(Berti): avoid unsigned underflow in timeliness comparison module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6320 opened Aug 2, 2026 by domingxperez Loading…
fix(Berti): remove unreliable PC override in PrefetcherWrapper module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6319 opened Aug 1, 2026 by domingxperez Loading…
ci: bump the github-actions group across 1 directory with 2 updates dependencies Pull requests that update a dependency file github_actions Pull requests that update GitHub Actions code module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc.
#6317 opened Jul 31, 2026 by dependabot Bot Loading…
1
fix(AtomicsUnit): if amo is unalign report *accessFault module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6316 opened Jul 31, 2026 by weidingliu Member Loading…
1
1
fix(WriteBuffer): read-write conflict on the same entry caused an error module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: code quality To make code more readable & maintainable
#6315 opened Jul 31, 2026 by sleep-zzz Contributor Loading…
1
fix(MMU) -COVE- : fix mpt walker bug module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#6314 opened Jul 30, 2026 by HaoyuanLiuHZPH Contributor Loading…
1
perf(rob): implement hybrid rob compression to support two slots in one entry module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs module: utility RTL utility note: do not merge (PR) For maintainer: do not merge this pull request yet note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6313 opened Jul 30, 2026 by Lemover Contributor Loading…
1
fix(StoreQueue): use the real forward mask for s2FullOverlap module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6312 opened Jul 30, 2026 by emiliengnr Loading…
1
1
fix(LoadUnit, StoreUnit): use PMM-normalized VA for triggers module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6311 opened Jul 30, 2026 by DFPMTS Loading…
1
fix(TLB): canonicalize PMM addresses for only-stage-2 translation module: documentation Improvements or additions to documentation module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6309 opened Jul 30, 2026 by DFPMTS Loading…
1
fix(MissQueue): secondary_ready should gate req_valid module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#6308 opened Jul 30, 2026 by jlong299 Contributor Loading…
1
fix(abtb): train counters on not-taken S3 predictions module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#6305 opened Jul 29, 2026 by CaoJiaming776 Member Loading…
6
fix(ifu): fix s1_instrCount calculation when an exception occurs module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#6301 opened Jul 28, 2026 by my-mayfly Collaborator Loading…
6
fix(mmu)-COVE- : fix bug for mpt cache module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#6300 opened Jul 28, 2026 by HaoyuanLiuHZPH Contributor Loading…
1
fix(mmu) -COVE-: reject out-of-range Smmpt addresses module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6299 opened Jul 28, 2026 by HaoyuanLiuHZPH Contributor Loading…
1
fix(zhujiang): fix gsim compile module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6287 opened Jul 27, 2026 by Ruomio Contributor • Draft
1
feat(vector): add support for Zvbc extension module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs note: do not merge (PR) For maintainer: do not merge this pull request yet note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6282 opened Jul 24, 2026 by marc-marcos Loading…
timing(Ftq,ICache): fix meta read port timing module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#6281 opened Jul 23, 2026 by TheKiteRunner24 Collaborator Loading…
4
feat(vector): new vector float-point multiplier/alu support by using scalar fp functionUnit in Yunsuan module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6280 opened Jul 23, 2026 by Squareless-XD Member Loading…
fix(zhujiang): fix gsim compile module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6279 opened Jul 23, 2026 by Ruomio Contributor • Draft
feat(prefetch): add L3 prefetch request path module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6274 opened Jul 23, 2026 by zzQGyy Contributor Loading…
2
fix(Frontend,TLB,CSR): frontend pc canonical check module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: do not merge (PR) For maintainer: do not merge this pull request yet topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6272 opened Jul 22, 2026 by ngc7331 Member Loading…
6
timing(Phr): fix the update timing of Phr during s1 and s3 module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#6263 opened Jul 21, 2026 by sleep-zzz Contributor Loading…
1
perf(l2pf): add F-POP prefetch controller module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6255 opened Jul 18, 2026 by Maxpicca-Li Member Loading…
1 task
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