Verilog Problems – RTL Design Practice

This repository contains Verilog problems and their solutions designed to improve hands-on RTL design skills.

It contains collection of Verilog-based RTL designs covering a range of digital design topics such as counters, finite state machines (FSMs), shift registers, and more.

Each module includes:

• Clean Verilog RTL implementation in file.v
• Simulation testbench in file_test.v
• Waveform and schematic screenshots documented in all_result.md

Tools Used

• Vivado - For synthesis, simulation, and schematic generation

Goal

To practice and demonstrate Verilog fundamentals through small, clean modules—targeted toward digital design and VLSI roles.