RISC-V-Single-Cycle-Processor

Single Cycle Processor written from scratch in SystemVerilog for executing the machine code of RISC-V ISA. RISC-V is an open standard instruction set architecture based on established reduced instruction set computer principles.

Instruction Types

The instruction types implemented in this project are:

• R-type
• I-type
• S-type
• B-type
• J-type
• U-type

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