|
18 | 18 | import zlib |
19 | 19 | import re |
20 | 20 | from dataclasses import dataclass, asdict |
21 | | -from typing import Optional |
22 | 21 |
|
23 | 22 | # --------------------------------------------------------------------------- |
24 | 23 | # Constants — must match panicdump.h |
@@ -162,34 +161,50 @@ def parse(raw: bytes) -> PanicDump: |
162 | 161 | # CFSR decoder — helps explain what caused the fault |
163 | 162 | # --------------------------------------------------------------------------- |
164 | 163 |
|
| 164 | +_UFSR_BITS = [ |
| 165 | + (9, "DIVBYZERO"), |
| 166 | + (8, "UNALIGNED"), |
| 167 | + (3, "NOCP (coprocessor fault)"), |
| 168 | + (2, "INVPC (invalid PC load)"), |
| 169 | + (1, "INVSTATE (invalid state)"), |
| 170 | + (0, "UNDEFINSTR (undefined instruction)"), |
| 171 | +] |
| 172 | + |
| 173 | +_BFSR_BITS = [ |
| 174 | + (7, "BFARVALID (BFAR holds address)"), |
| 175 | + (5, "LSPERR (FP lazy stack)"), |
| 176 | + (4, "STKERR (stack push fault)"), |
| 177 | + (3, "UNSTKERR (stack pop fault)"), |
| 178 | + (2, "IMPRECISERR (imprecise data bus)"), |
| 179 | + (1, "PRECISERR (precise data bus)"), |
| 180 | + (0, "IBUSERR (instruction bus fault)"), |
| 181 | +] |
| 182 | + |
| 183 | +_MMFSR_BITS = [ |
| 184 | + (7, "MMARVALID (MMFAR holds address)"), |
| 185 | + (5, "MLSPERR (FP lazy stack MPU)"), |
| 186 | + (4, "MSTKERR (stack push MPU)"), |
| 187 | + (3, "MUNSTKERR (stack pop MPU)"), |
| 188 | + (1, "DACCVIOL (data access violation)"), |
| 189 | + (0, "IACCVIOL (instruction access violation)"), |
| 190 | +] |
| 191 | + |
| 192 | + |
165 | 193 | def decode_cfsr(cfsr: int) -> list[str]: |
166 | | - bits = [] |
167 | | - # UFSR (bits 31:16) |
168 | | - ufsr = (cfsr >> 16) & 0xFFFF |
169 | | - if ufsr & (1 << 9): bits.append("DIVBYZERO") |
170 | | - if ufsr & (1 << 8): bits.append("UNALIGNED") |
171 | | - if ufsr & (1 << 3): bits.append("NOCP (coprocessor fault)") |
172 | | - if ufsr & (1 << 2): bits.append("INVPC (invalid PC load)") |
173 | | - if ufsr & (1 << 1): bits.append("INVSTATE (invalid state)") |
174 | | - if ufsr & (1 << 0): bits.append("UNDEFINSTR (undefined instruction)") |
175 | | - # BFSR (bits 15:8) |
176 | | - bfsr = (cfsr >> 8) & 0xFF |
177 | | - if bfsr & (1 << 7): bits.append("BFARVALID (BFAR holds address)") |
178 | | - if bfsr & (1 << 5): bits.append("LSPERR (FP lazy stack)") |
179 | | - if bfsr & (1 << 4): bits.append("STKERR (stack push fault)") |
180 | | - if bfsr & (1 << 3): bits.append("UNSTKERR (stack pop fault)") |
181 | | - if bfsr & (1 << 2): bits.append("IMPRECISERR (imprecise data bus)") |
182 | | - if bfsr & (1 << 1): bits.append("PRECISERR (precise data bus)") |
183 | | - if bfsr & (1 << 0): bits.append("IBUSERR (instruction bus fault)") |
184 | | - # MMFSR (bits 7:0) |
185 | | - mmfsr = cfsr & 0xFF |
186 | | - if mmfsr & (1 << 7): bits.append("MMARVALID (MMFAR holds address)") |
187 | | - if mmfsr & (1 << 5): bits.append("MLSPERR (FP lazy stack MPU)") |
188 | | - if mmfsr & (1 << 4): bits.append("MSTKERR (stack push MPU)") |
189 | | - if mmfsr & (1 << 3): bits.append("MUNSTKERR (stack pop MPU)") |
190 | | - if mmfsr & (1 << 1): bits.append("DACCVIOL (data access violation)") |
191 | | - if mmfsr & (1 << 0): bits.append("IACCVIOL (instruction access violation)") |
192 | | - return bits |
| 194 | + ufsr = (cfsr >> 16) & 0xFFFF |
| 195 | + bfsr = (cfsr >> 8) & 0xFF |
| 196 | + mmfsr = cfsr & 0xFF |
| 197 | + result = [] |
| 198 | + for bit, name in _UFSR_BITS: |
| 199 | + if ufsr & (1 << bit): |
| 200 | + result.append(name) |
| 201 | + for bit, name in _BFSR_BITS: |
| 202 | + if bfsr & (1 << bit): |
| 203 | + result.append(name) |
| 204 | + for bit, name in _MMFSR_BITS: |
| 205 | + if mmfsr & (1 << bit): |
| 206 | + result.append(name) |
| 207 | + return result |
193 | 208 |
|
194 | 209 | # --------------------------------------------------------------------------- |
195 | 210 | # Report rendering |
|
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